Low Power and High Performance Dynamic CMOS XOR/XNOR Gate
نویسندگان
چکیده
A hybrid network is proposed in dynamic CMOS XOR/XNOR gate to avoid signal skew and reduce the power consumption. Compared to the standard N type dynamic gate leakage power, dynamic power and layout area of the novel XOR/XNOR gate are reduced. In this paper we studied different technologies, their merits and demerits. Comparison of different technologies is completely on the basis of leakage power, dynamic power, layout area and performance. Also the inputs and clock signals combination static state dependent leakage characteristics of three dynamic CMOS XOR/XNOR gates are analyzed thoroughly. Keywordshybrid; signal skew; leakage power; dynamic power; layout area;clock signal.
منابع مشابه
Low power and high performance dynamic CMOS XOR/XNOR gate design
Article history: Available online 17 February 2011 Keyword: Dynamic XOR/XNOR Gate Leakage Power Variation 0167-9317/$ see front matter 2011 Elsevier B.V. A doi:10.1016/j.mee.2011.02.068 ⇑ Corresponding author. Tel.: +86 15001166864. E-mail address: [email protected] (J. A hybrid network technique is proposed in dynamic CMOS XOR/XNOR gate to reduce the power consumption, save the layout...
متن کاملAnalysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology
As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...
متن کاملComparative Performance Analysis of XOR- XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS...
متن کاملA New design of 1-bit full adder based on XOR-XNOR gate
In this paper propose a new high performance 1 bit full adder cell using XOR/XNOR gate design style as well as lower power consumption. Simulation results illustrate the superiority of the resulting proposed adder against conventional 1-bit full-adder in terms of power consumption improvement performance (98% of 10T, 47% of 14T & 16T), propagation delay and PDP. We have performed simulations us...
متن کاملDesign of a low power and high performance digital multiplier using a novel 8T adder
Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices .The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency.Multiplier is the most commonly used circuit in the digital devices. Multiplication...
متن کامل